Suppose you need a fast serial link between one low-end FPGA and another. Which protocol would you use? You might consider SPI or I2C, but they both use multiple wires. You could choose asynchronous serial / RS-232, but then you need accurate clocks. Cheap FPGAs have built-in clock oscillators, but they are not very accurate, especially over the full temperature range.
A simple solution is to use PWM: it's self-timed (so only needs a single wire), and does not require accurate clocks to decode. Compared with a high speed serdes (for example for Gigabit Ethernet or PCI-e), the decoder is simple- it's basically just an up/down counter with some surrounding logic.
To transmit a zero, send a 33% duty-cycle pulse. To transmit a one, send a 66% duty-cycle pulse. End of packet (or end of word) is signaled by no pulse or an idle line. Start of packet is the first pulse that ends an idle line.
Now how do you decode? Clock a counter at least 3x the bit-rate. When the input is high, count up. When the input is low, count down. A the end of the bit cell (determined using an edge detector), the sign bit of the counter is the decoded bit. How do you detect the end of a packet? The counter is measuring the bit-time, so if the counter reaches, say, double the magnitude of the previous bit-time, the end of the packet has been reached.
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